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IP Products

Over the years, our designers have developed a wide range of analog, digital and memory circuits. We offer some of our most useful macro cells as “IP” (Intellectual Property). They include memory (EEPROM, SRAM, ROM) and an assortment of analog functions. A sample of our available cells is listed below. For more information, please contact CSS.

 

16K EEPROM

Low Power 2K x 8 EEPROM Macro Cell

This nonvolatile memory is a 16K bit EEPROM macro cell, organized 2K by 8. It may be re-configured for sizes from 1K to 64K bits and from 8 to 32 bits per word. It features low power, a wide supply range, a synchronous read mode and three programming modes: Page Erase, Block Erase and Page Write. A data register is included that holds eight bytes (one page) of data. During a Page Write operation, the contents of this register are programmed into the selected row (page) of memory. This memory macro cell is designed for AMI’s 0.5 micron, CMOS process. For more information, please refer to the following documents or contact CSS.

Type	File Name	Action
	CSS_2Kx8_EEPROM_Spec (164K)	Info available on request
	CSS_EEPROM_App_Note1_Test_Modes (117K)
	CSS_EEPROM_Size_Calculator_C5 (50K)

 

High Density NV Register

Micro-Power Nonvolatile Register (High Density Version)

This EEPROM memory macro is a nonvolatile register that can be configured for 8 to 64 bits.  It is implemented with CSS’s High Density NV Latch cell that features a novel, high voltage level shifter to significantly reduce its area.  Read mode current is < 1uA.  Numerous serial and parallel interface options for entering data and reading out the contents of the NV register are available.  This memory macro cell is designed for AMI’s 0.5 micron, CMOS process.  For more information, please refer to the following documents or contact CSS.

Type	File Name	Action
	CSS_High_Density_NV_Register_Spec (169K)	Info available on request
	CSS_HD_NV_Register_App_Note1 (105K)
	CSS_NV_Register_Size_Calculator_C5 (84K)

 

NV Register

Micro-Power Nonvolatile Register (Classic Version)

This EEPROM memory macro is a nonvolatile register that can be configured for 8 to 64 bits. It is implemented with CSS’s Classic NV Latch cell that features a single cycle store function. Read mode current is < 1uA. Numerous serial and parallel interface options for entering data and reading out the contents of the NV register are available. This memory macro cell is designed for AMI’s 0.5 micron, CMOS process. For more information, please refer to the following documents or contact CSS.

Type	File Name	Action
	CSS_Classic_NV_Register_Spec (176K)	Info available on request
	CSS_Classic_NV_Register_App_Note1 (105K)
	CSS_NV_Register_Size_Calculator_C5 (84K)

 

VPP Generator

EEPROM Program Voltage Generator

This support circuit provides the high positive voltage required to program the EEPROM memory cells. It generates approximately +20V with a multi-stage charge pump. It includes a high frequency oscillator and voltage regulator. This circuit is designed for AMI’s 0.5 micron, CMOS process. For more information, please refer to the following specification or contact CSS.

Type	File Name	Action
	CSS_VPP_Generator_Spec (169K)	Info available on request

 

SRAM (C5 Process)

Low Power, High Density Static RAM

This memory macro is a configurable static RAM. Its architecture will support a wide array of memory sizes. It is optimized for low power and high density. It features a wide supply range (1.25V to 5.5V), a synchronous read mode and dual data I/O ports. This macro cell is designed for a 0.5 micron, CMOS process. For more information, please refer to the following documents or contact CSS.

Type	File Name	Action
	CSS_Low_Power_SRAM _C5 (156K)	Info available on request
	CSS_SRAM_Size_Calculator _C5 (84K)

 

SRAM (C3 Process)

Low Power, High Density Static RAM

This memory macro is a configurable static RAM. Its architecture will support a wide array of memory sizes. It is optimized for low power and high density. It features a wide supply range (1.25V to 5.5V), a synchronous read mode and dual data I/O ports. This macro cell is designed for a 0.35 micron, CMOS process. For more information, please refer to the following documents or contact CSS.

Type	File Name	Action
	CSS_Low_Power_SRAM_Spec _C3 (134K)	Info available on request
	CSS_SRAM_Size_Calculator_C3 (50K)

 

ROM (C5 Process)

Low Power, High Density ROM

This memory macro is a mask programmable ROM. Its architecture supports a wide array of memory sizes. It is optimized for low power and high density. It features a wide supply range (1.25V to 5.5V) and a synchronous read mode. This macro cell is designed for a 0.5 micron, CMOS process. For more information, please refer to the following documents or contact CSS.

Type	File Name	Action
	CSS_Low_Power_ROM_Spec_C5 (125K)	Info available on request
	CSS_ROM_Size_Calculator_C5 (50K)

 

ROM (C3 Process)

Low Power, High Density ROM

This memory macro is a mask programmable ROM. Its architecture supports a wide array of memory sizes. It is optimized for low power and high density. It features a wide supply range (1.25V to 5.5V) and a synchronous read mode. This macro cell is designed for a 0.35 micron, CMOS process. For more information, please refer to the following documents or contact CSS.

Type	File Name	Action
	CSS_Low_Power_ROM_Spec_C3 (133K)	Info available on request
	CSS_ROM_Size_Calculator_C3 (50K)

 

Amplifier “AB_P1E”

Pch Input, Class AB Output Amplifier

This analog macro cell is a single supply, general-purpose operational amplifier. It contains a folded cascode, PCH differential input stage and a class AB output stage. The common mode input range extends from GND to (VPOS – 1.0V). The output stage is capable of driving off-chip loads of 1KΩ and 50pF. It is internally compensated and is unity gain stable. An “Enable” input is included to allow the amplifier to be placed into a low (~ zero) power mode.

Type	File Name	Action
	CSS_Amplifier_AB_P1E_Spec (186K)	Info available on request

 

100 KHz Crystal Oscillator

Low Power 100KHz Crystal Oscillator

This analog macro cell is a 100KHz crystal oscillator circuit. It includes an integrated resistor and capacitor network (CG, CD & RA) so no external components are required. Each internal component may be adjusted to optimize the oscillator for various crystal parameters and lowest possible power and/or lowest operating voltage. The gm of the linear amplifier is also adjustable. This circuit includes a low power buffer with hysteresis to provide glitch free edges, suitable for digital clock signals. A “Disable” input is provided to halt the oscillator and place it in a low power state.

Type	File Name	Action
	CSS_100KHz_Xtal_Osc_Spec (121K)	Info available on request

 

32 KHz Crystal Oscillator

Low Power 32KHz Crystal Oscillator

This analog macro cell is similar to the 100KHz version but designed to operate with a 32KHz crystal. See “XTO_100K” for more details.

Other Macro Cell Functions:

• Bandgap Voltage References
• Low TC, Bias Current Generators
• Micropower, Rail-to-Rail Input Comparator
• High Voltage Amplifiers (12V)
• Ultra Low Power Relaxation Oscillators
• DAC’s (4, 6, 8 & 10 bit)
• Digital Trim Pot’s with EEPROM
• Digital Standard Cell Library

For more information, please contact CSS