CSS Mixed Signal ASIC Solutions

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Articles from the November 2014 Newsletter


Article #1
Ultra-Low Power Supply Controller ASICs

Low power consumption is of paramount importance in scenarios where uninterrupted use is required for maximum efficacy and minimum inconvenience as in medical devices, wearable or portable electronic products and internet-of-things (IoT) devices. Replacement of a battery in mid-use of a therapy session or data-acquisition period, for example, is not an option in such devices.

CSS has developed key design techniques incorporated within an application specific integrated circuit (ASIC), that enable us to maximize the use of battery charge by increasing the efficiency of the power delivery mechanism which is crucial to such devices. These devices typically require a switch-mode regulator such as a step-up or Boost/Flyback converter or step-down/Buck regulator. Step-up converters are used so that higher voltages than the battery can be attained for the operation of certain modes (neuro-stimulation, sensor operation, etc.). Step-down or Buck converters that provide voltages lower than that of the battery may be used to optimize the power consumption of the device. This is because many circuits only rely on the supply of a certain amount of current as long as the voltage itself is above a certain value.   Using a linear or LDO regulator to create the lower voltage does not lower the power consumption as it only results in power loss across the regulator itself. For example, given a 3.6V battery that supplies 200 uA and a linear regulator output of 1.2V (to power circuits that can operate off 1.2V) means that the battery provides 720uW of power of which 480 uW is dissipated across the linear regulator. With only 240 uW finally delivered to the circuits, the linear regulator approach at best achieves an efficiency of 33%. A switch-mode regulator such as a Buck converter may hence offer a more efficient implementation. However, both step-up and step-down converters can themselves consume a large percentage of the energy budget, especially in applications where supply current usage is below 100 uA.

By using novel circuit techniques within the ASIC, power that is usually wasted in the voltage conversion process can actually be re-harnessed to sufficiently offset the operational current of the converters themselves. This is very important in low-current applications, since without such techniques, converter efficiency is usually very poor at low load currents as shown in the graph below for a Buck-converter. Devices that operate with currents below 20 uA have been successfully implemented using these techniques, thereby making them ideal for medical devices, wearable/portable electronics and the IoT arena.


Article #2
The Engineers of CSS – Allan Stewart

CSS has a great staff of engineers, but since they are often working “behind the scenes” they may not be well known outside the Company. This Blog, featuring Allan Stewart, is a continuation in the series of interviews titled “The Engineers of CSS” which will hopefully help everyone to know them much better.

Allan Stewart, Engineer at CSS

Allan Stewart

Here is a little bit about Allan in his own words.

I graduated with a BSEE from the University of Strathclyde, Glasgow Scotland in 1975 and began working as a circuit design engineer for Telecommunications, Defense, and Medical companies in the UK.  I joined Burroughs/Unisys in 1984 to work on circuit board development, and transferred to Orange County to take up a circuit design manager position in1987.  I joined Adaptec in 1996 responsible for Disk Drive servo controller ASIC development, and moved on to TI Storage Products where I also became involved in Disk Drive Read channel development.  I joined Calimetrics as Director of ASIC development in 2000 – working on multi-level CD and DVD technology development storage products.  I became an independent consultant in 2003 working on a number of projects developed jointly by Treehouse Design in Colorado and Chronicle Technology in Irvine.  I began working exclusively for Chronicle starting 2011, initially developing a 1.5Gbs SerDes interface for High Speed Video applications, and latterly worked on the 65nm and 28nm Bitcoin devices for Butterfly Labs.


CSS: You have a very impressive background as indicated in your history as provide above. What were the most interesting or technically challenging projects you have worked on during your career?

Allan:  From a technically challenging perspective I did a 1.5 – 2.5 Gbit/s SerDes with Chronicle just prior to the 65nm bitcoin chip, which was quite challenging. It combined high frequency PLL work along with some high speed digital requirements, allowing me to re-visit some of my old circuit board design challenges from earlier in my career.

CSS: You started working at Chronicle Technologies prior to the merger of Chronicle and CSS in 2013. What do you feel have been the advantages of the merger?

Allan:  I think the benefits were the result of each group having different strengths in terms of the depth of their capability.  Chronicle had more depth in design and layout, CSS brought the production test capability and ISO certification.  The result was not a significant overlap in skills and a good combination of the skills for ASIC design, test and manufacturing.

CSS: I know that you were a key person in the recent development of the bitcoin chips. Both the 65 nm and the 28 nm chips were successful complex digital designs. The 28 nm chip was an especially large ASIC, with 5.5 billion transistors!   What do you remember most about these developments?

Allan:  The 65nm was probably the more difficult of the two designs.  We had to figure out the architecture – we experimented with 5 or 6 different technologies trying to get the combination of speed and power we desired.

The test development was a challenge also – this was really the first time CSS and Chronicle had worked closely together – so it was a learning experience – but in the end I think a very successful one.

From a design perspective, the 28nm was more straightforward. We identified & designed the
cells that needed to be improved to meet our new targets.  However. since this chip increased the number of Hash Engines from 16 (on the 65nM design) to 1024, it was huge and consumed 350Watts power.  These were the challenges.