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ASIC Glossary of Terms

A B C D E F G H I J K L M N O P Q R S T U V W X Y Z All

A device or devices randomly chosen from a lot of material. Sampling assumes that randomly selected devices will exhibit characteristics during testing that are typical of the lot as a whole.

Sampling Plan:
A statistically derived set of sample sizes, accept numbers, and/or reject numbers which will confirm that a given lot of materials meets established AQLs or LTPDs.

Schematic Drawing:
Diagram of an electrical or mechanical system.

Schottky barrier:
A potential barrier formed between a metal and a semiconductor, frequently used in the creation of Schottky diodes.

100% testing of a device, as opposed to sampling.

Scribe lane:
The area separating two adjacent dice on a wafer through which the scribing tool will pass during the separation of the wafer into individual dice.

The process whereby the lid is fastened onto a cavity (or hermetic) type semiconductor device. Sealing methods include solder (whereby a metal lid is soldered to a metal seal ring), weld (where a metal lid is welded to a metal package base), and glass (or ceramic) seal (where a ceramic lid is fastened to a ceramic base with reflowed glass).

Scanning Electron Microscope Inspection, which allows magnification several magnitudes higher than could be achieved with an optical microscope. A scanning electron microscope is typically capable of resolution to 250 A or better and magnification of greater than 20000X.

An element, such as silicon or germanium, that is the intermediate in electrical conductivity between the conductors and the insulators.

Application of a unique alphanumeric identifier to each unit of a lot of devices to afford traceability to variables data, individual radiographs, etc.

Silicon gate:
An MOS process fabricated with a polysilicon material as the gate electrode.

symbol Si, is the most commonly used basic building block of integrated circuits. Silicon is a semiconductor, which means that its electrical behavior is between that of a conductor and an insulator at room temperature. With the proper addition of dopant elements, p-n junctions can be formed on silicon. Useful electronic components and integrated circuits can be built from p-n junctions. Silicon is obtained by heating silicon dioxide (SiO2), or silica, with a reducing agent in a furnace. Silicon dioxide is the main component of ordinary sand.

Single-in-line package:
A package (either hermetic or molded) with all its leads emanating from one side of the package.

Abbreviation for single-in-line package.

Surface Mounted Packaging.

Soft error:
An error of a nonpermanent nature introduced into a cell or cells of a memory device as a result of either voltage or current transients or radiation exposures. Although soft errors may be corrected, the data previously stored in the cell may not be retrievable.

The instructions which program or sequence the functioning of the hardware of a device or system. These instructions may be contained internally (in ROM, for example) or externally (on tape, disc, or any other suitable memory medium).

Solder dip:
Dipping of the leads of devices into molten solder in order to later facilitate soldering of the devices to circuit boards. Sometimes inaccurately referred to as "tin dip.,

Solder seal:
Semiconductor device sealing accomplished by soldering a metal lid to a metal seal ring.

Solderability testing:
Immersion of the leads of sample devices in solder, followed by visual inspection to determine that the quality of the finish is such that it will accept an even coating of solder.

Source control drawing:
Similar to a specification control drawing except that purchase of the specified devices from manufacturing sources other than those listed on the drawing is prohibited.

Source inspection:
Surveillance or inspection by a customer's quality representative or by a government inspector at the vendor's facility of material being assembled or screened by that vendor.

Simulation Program with Integrated Circuit Emphasis, standard for electronic circuit simulation.

Small Scale Integration. SSI devices are those that contain less than 12 gate equivalents.

Stabilization bake:
Placement of devices in a chamber at elevated temperature (normally 150°C) without electrical bias in order to test the construction of the devices.

Standard Product
an integrated circuit that implements functions that appeals to a wide market. As opposed to ASICs that combine a collection of functions and designed by or for one customer.

Statistical quality control:
A quality control system utilizing statistical analysis of process defect data to detect quality trends on a real time basis.

The physical material upon which an integrated circuit is fabricated or assembled. For a monolithic device, this would be the silicon of the chip; for a hybrid it would be the alumina or ceramic surface upon which the die and other elements are deposited.

Surface mounted packaging:
Semiconductor packages mounted on the surface of a printed circuit board or other substrate material.

Surface states:
Extra donors, acceptors, or traps, usually undesired, which may occur on a semiconductor surface because of crystal imperfections or contamination. These may vary with time.