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ASIC Glossary of Terms

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An MOS process in which MOS transistors are formed by bridging two adjacent P-type diffusions (source and drain) with a dielectric (gate). When the source and the substrate are grounded and a negative voltage is applied to the gate, a conductive sheet of positive charge (P-channel) is created in the surface of the substrate under the dielectric.

Semiconductor material in which the majority carriers are holes and are therefore positive.

Packaging density:
For integrated circuits, the number of semiconductor elements per unit area of chip size, frequently expressed in terms of number of gate equivalents.

Parasitic device or element:
An interaction between diffused circuit elements. A good example of a parasitic would be the collector series resistance (RSAT) of a transistor and the associated capacitance of the collector-to-substrate junction.

Particle Count:
A measurement scale for gas or liquid cleanliness, normally stated in parts per cubic foot. For example, a Class 10 working area would be one which contained no more than 10 particles greater than one micron in size per cubic foot of air.

The surface coating of the die (usually thermally grown silicon dioxide, Si02) through which contact and diffusion windows are opened.

Passive device:
Devices such as resistors or capacitors which have no amplification or control characteristics.

Perfect Defect Allowable, the maximum percentage of a lot which may fail a 100% screening step without rejecting the lot. The PDA is predicted on the possibility that a failure mechanism which appears in an abnormally high percentage of a lot might appear at a later time in the balance of the lot. It should, therefore, not be used for screens where all defective devices can be observed and removed (such as internal visual or X-ray).

Peripheral device:
A device within a microprocessor device family whose function is required to support the operation of a CPU.

The listing or diagramm description of the functions assigned to the various package pins of a semiconductor device.

Small localized areas in the oxide layer with low dielectric strength, usually as a result of contamination.

Planar structure:
A flat-surfaced device structure with the junctions terminating on a single plane.

PNP transistor:
A junction transistor constructed by placing an N-type base between a P-type emitter and a P-type collector. The emitter is normally positive with respect to the base and the collector is normally negative with respect to the base.

Parts-per-million. A measurement scale for defect rates in components or impurity levels in materials.

Electrical test of semiconductor devices at the wafer level, so named because a metal probe is used to make electrical contact with each of the device's bonding pads.

Programmable Read-Only Memory. A memory device whose stored data content is established on an individual device basis through a programming process (usually involving the blowing of fuse links on the surface of the die).Unlike EPROMs and EEPROMs, PROMs cannot be erased and reprogrammed.

Protective device:
A circuit element fabricated on a semiconductor device (usually adjacent to the device input) for the purpose of protecting portions of the device circuitry from transient overstress. A good example of a protective device would be an input diode on a CMOS device, which absorbs electrostatic discharge to prevent that discharge from rupturing the gate oxide.

A functional device for verification of the Integrated Circuit.