Average Quality Level-The maximum acceptable reject percentage on the average for all outgoing lots.
Acceptable Quality Level-The maximum percent defective that can be considered acceptable as an average for all lots screened. The sample size used with a given AQL will prevent acceptance of 95% of all lots having a greater percent defective.
Application Specific Integrated Circuit. A custom or semicustom integrated circuit, such as a cell or gate array, created for a specific application. The complexity of ASICs typically requires significant use of CAD techniques.
Application Specific Standard Product, An ASIC chip that is designed as a generic device for a particular market.
Acceptance Test Plan-A document developed for the purpose of detailing all of the testing involved in device and/or lot acceptance.
Automatic Test Pattern Generation.  Test SCAN vectors are typically generated by ATPG.
Active circuit
That area of a die which contains all functional circuit elements.
Active device
A device which, when subjected to a current or voltage, exhibits either gain (amplification) and/or control characteristics, or a device which converts input signal energy into output signal energy through interaction with the energy from an auxiliary source(s).
Analog device
A microcircuit in which the output is a mathematical function of the input.
Angstrom (A)
A unit of length. 104Å = 1 micron or 1010Å = 1 m (meter).
The functional design of a complex component, circuit or system, including both its hardware and its compatibility with external hardware and software.
The functional design of a complex component, circuit or system, including both its hardware and its compatibility with external hardware and software.
Built-In Self-Test.  Subcircuitry designed into a circuit to allow that circuit to test itself either at a predetermined interval or upon external command.
Back end
A slang term frequently applied to the assembly and test portion of the semiconductor manufacturing process (see Front end).
Fine grinding or polishing of the bottom side of wafers prior to diffusion to reduce wafer stress and provide uniform thickness and planarity.
A detailed definition of a device’s electrical and mechanical configuration, assembly, processing and testing used as a base from which to track subsequent changes
Binary logic
Logic using two logic states (ON and OFF, or Logic “0” and Logic “V).
Devices or processes in which current-carrying areas and substrates are of different polarities (such as the PNP and NPN transistors used to form TTL circuits). Both holes and electrons are transported in bipolar devices. Some technologies, such as BI-FETTM, combine bipolar and unipolar elements.
One binary digit. In binary arithmetic all data is represented by 1’s and 0’s. In a semiconductor device, these logic levels are created by the presence or absence of electrons in a cell.
Block diagram
A system diagram in which the principal parts or functions are represented by blocks connected by lines which show the relationships of the blocks.
Bond pull
Pulling of the bond wires to destruction to determine the strength of the bonds.
Bonding pad
An expanded metallization area on the surface of a die where the bonding wire will be placed.
The application of electrical biases to a device while operating it at an elevated temperature (usually 125°C), normally as a 100% screening test. Standard burn-in durations are 160 hours for Class B devices and 240 hours for Class S. This test is designed to “weed out” devices subject to infant mortality or excessive parametric drift.
Computer Aided Design. The use of computer automation in the implementation of all or a portion of a design for a complex circuit.
CMOS (Complementary Metal-Oxide Semiconductor)
An MOS fabrication technology in which both P-channel and N-channel devices are fabricated on the same die.
Central Processing Unit.
Capacitive decoupling
Protection of a device from voltage transients or “spikes”, or the isolation of a device from an AC voltage by decoupling the voltage source(s) to ground through a capacitor.
Cell array
An integrated circuit formed through the positioning and interconnection of a number of functional blocks, or cells, on a die.
Certificate of conformance
A certificate provided by a manufacturer’s QA department to the procuring activity with a lot of material to confirm that all material in the lot conforms with all applicable specifications.
A region of surface conduction opposite in type from that expected from the bulk doping. Channels are sometimes introduced unintentionally by surface ionic contamination. The type of channel (P or N) will be determined by the type of majority carrier introduced into the channel.
Electrical testing performed for the purpose of determining typical device performance characteristics and/or parametric limits.
Charge carrier
A carrier of electrical charge within the crystal of a solid state device, such as an electron or a hole.
A common term used for an Integrated Circuit (IC).
Chip carrier
A leadless package used in the construction of both hybrids and boards. The chip carrier has a body configuration similar to a flat pack, but electrical connection is made through contacts on the package base rather than through conventional leads.
Configuration control
A requirement that a vendor notify the procuring and/or qualifying activity of a change in product manufacture or test. In some cases, the requirement will include delay of change implementation until after formal approval of the change.
The opening in the surface passivation through which the device metallization makes contact with the circuit elements.
Current density
The amount of current flow per unit of cross-sectional area within device metallization. For example, a 1 mA current flowing through a metallization stripe that is 3 wide and 1 thick would result in a current density of 0.33 x 105 A/cm2.
Design for Test.  Design methodologies intended to allow circuitry to be tested in production.
Abbreviation for Dual-In-line Package.
Delay Lock Loop.  Mixed-signal block used to adjust the phase of a clock signal.  Useful in clock recovery.
Design Rule Checks
Device Under Test.
Data log
The recording, by individual device serial number, of the actual parametric values measured for that device at a specific electrical test point. Read-and-record can be done for device characterization, drift (delta) measurement, or temperature coefficient computation.
Date code
A three- or four-digit number identifying the inspection lot from which material was selected. The first two digits (or first digit for a three-digit code) identify the year, the last two the week. Normally, the date code is based upon week of seal for the first sublot of the inspection lot.
Decapsulation is a chemical etching technique for opening IC plastic packages in order to expose their internal components for examination. Although physically destructive in nature, the process leaves the die, bond pads, and wire bonds intact.
A limit applied to the amount of parametric drift that a unit may display across a screen or series of screens (usually applied to burn-in).
Depletion layer
The region in a semiconductor where essentially all charge carriers have been swept out by the electrical field which exists there.
Destructive testing
Sample testing which is sufficiently severe to make further use of the tested devices questionable. Devices subjected to destructive testing may not actually be destroyed, but are sufficiently degraded that they should not be used in any system.
Process of reducing a wafer to individual dies
A single square or rectangular piece of silicon into which a specific semiconductor circuit has been diffused.
Die size
Die size refers to the physical surface area of the individual die and is typically measured in square millimeters (mm^2). In essence a “die” is really a chip, but it is only referred to in this way when discussing physical chip parameters and manufacturing issues.
Die sort
Electrically, a probe to sort the die on a wafer according to predetermined electrical limits. Visually, a sort into Condition A, Condition B, or commercial grade die.
Dielectric isolation
A semiconductor fabrication process in which each circuit element is enclosed within an oxide barrier that completely isolates the element from all other diffused elements.
Diffused area
A portion of the die where impurities have been diffused into the surface of the silicon at high temperature to change its electrical characteristics through the creation of a concentration of N or P charge carriers.
Digital device
A microcircuit in which the inputs accept logic states (such as 0 or 1) and convert these to logic states at the output(s) according to a predetermined set of logic equations or function tables.
A semiconductor or semiconductor die containing only one active device, such as a transistor or a diode.
Distributed processing
In digital data systems, the utilization of a number of dedicated processors distributed throughout the system for the purpose of doing computation locally.
The introduction of an impurity into the crystal lattice of a semiconductor to modify its electrical properties by creating a concentration of N or P carriers.
Dual-in-line package
A package (either hermetic or molded) with its leads emanating from both sides of the package, then turning downward.
Electronically Alterable Read Only Memory Functionally similar to EEPROM.
Electronically Erasable-Programmable Read Only Memory-A memory device whose content can be established through a programming process (usually the tunneling of electrons across a thin layer of silicon dioxide) to a floating gate. Each memory cell of an EEPROM can be individually erased by imposing a voltage to reverse the flow of electrons to move them away from the floating gate. That cell can then be reprogrammed. Both programming and erasing can be performed without removal of the device from the system in which it is used.
Erasable Programmable Read Only Memory-A memory device whose content can be established through a programming process (usually hot electron injection) and can be totally erased by exposure to ultraviolet light for sustained periods. When properly erased, the device can be reprogrammed.
Electrostatic Discharge
Effectivity date
The date upon which a new military document or a new revision of an existing document goes into effect.
Particle migration in aluminum thin-film or polysilicon conductors at grain boundaries as a result of high current densities. Electromigration can lead to either an open circuit condition in a conductor or a short between adjacent connectors.
Electrostatic discharge
The discharge of accumulated static charge (typically of high voltage at low current) from one collector to another, usually by jumping the air gap between the two. Element: A topographically distinguishable part of a microcircuit which contributes directly to its electrical characteristics.
Electrostatic sensitivity
Susceptibility to damage or degradation as the result of subjection to electrostatic discharge. Typically much higher for MOS devices than for bipolar.
The process of encapsulating or “potting” a molded device.
One of the final steps in processing a wafer during which conductive metal, usually aluminum, is deposited on the surface of the wafer in order to provide electrical interconnection of the various active elements on each die. Metallization may also be accomplished through sputtering.
The field-effect transistor (FET) is a type of transistor that relies on an electric field to control the shape and hence the conductivity of a channel of one type of charge carrier in a semiconductor material. FETs are sometimes called unipolar transistors to contrast their single-carrier-type operation with the dual-carrier-type operation of bipolar (junction) transistors (BJT).
Focused Ion Beam (FIB) technologies, testing and failure analysis of microelectronic devices,
Failure Analysis
A post-mortem examination of failed devices for the purpose of verifying the reported failure and identifying the mode or mechanism of failure. Failure analysis techniques may range from simple electrical and/or visual examination to some of the more advanced techniques of physics, metallurgy, and chemistry.
Failure rate
The calculated rate at which device failures will occur within a total device population.
Fault isolation diagnostics:
A feature (normally associated with built-in test) that allows identification of a malfunctioning subcircuit or circuits within a complex device.
Flat package
A thin package with ribbon leads coming out opposite sides of the package.
Foreign material
Any material that is foreign to a microcircuit or any non-foreign material that is displaced from its original or intended position within a microcircuit package.
Front end
A slang term often applied to the wafer fabrication portion of the semiconductor manufacturing process.
Gallium Arsenide (GaAs)
A semiconductor base material whose high electron mobility has led it to be used in the fabrication of high-speed circuits. GaAs circuits are not considered as easy to manufacture as silicon circuits.
Gate array
An integrated circuit containing a large number of gates that can be interconnected in any number of combinations to satisfy specific individual applications.
Gate equivalent
The basic unit of measure for digital circuit complexity, based upon the number of individual logic gates that would have to be interconnected to perform the same circuit function.
Gate oxide
A thin film of dielectric oxide material bridging the source and drain regions of an MOS semiconductor.
Generic data
Qualification or quality conformance data on devices from the same generic product family as the device shipped.
Generic family
A group of devices manufactured and assembled on the same line(s), using the same processes and materials, and designed to perform the same basic function (e.g., operational amplifiers, TTL gates, etc.).
see Passivation
The High Temperature Operating Life (HTOL) or steady-state life test is performed to determine the reliability of devices under operation at high temperature conditions over an extended period of time.
The physical elements and interfaces that constitute a component or system.
High Impedance (Z).  Usually refers to state of an I/O driver or analog load.
High temperature storage
A high temperature (150°C typically) bake performed for an extended period (usually 1000 hours) without electrical power applied.
The absence of a valence electron in a semiconductor crystal. The movement of a hole is equivalent to the movement of a positive charge.
Input/Output.  Typically refers to digital pins that can b configured as input, output, or tristate.
Abbreviation for integrated circuit.
Quiescent supply current. Static current measurement taken at multiple test vector locations.
Input Current.
Implementation date
The date by which a new military document or a new revision of an existing document must be implemented by those to whom its requirements apply. This date may be different than and later than the effectivity date.
A cylindrical piece of semiconductor material from which individual wafers will subsequently be sliced.
Actual performance of a screening step, as opposed to surveillance.
Insulating layer
A dielectric layer used to isolate multilevel conductive and resistive material or to protect top level conductive resistive material.
Integrated circuit
A semiconductor or semiconductor die containing multiple elements (which may be located on the die or on a hybrid substrate) which act together to form the completed device circuit.
The metallization connecting two or more active elements on the surface of a die; also, the wires connecting the die to the package leads.
Joint Test Access Group.  IEEE 1149.1 Boundary Scan.  Used to test interconnectivity on PCB or sub-blocks in IC.
The boundary between a P-region and an N-region in a silicon substrate.
Key Product Characteristics
Liquid Crystal Display, A display technology that uses rod-shaped molecules (liquid crystals) that flow like liquid and bend light.
Large Scale Integration-LSI devices are generally accepted to be those that contain between 100 and 1000 gate equivalents, or other circuitry of similar complexity.
Layout Versus Schematic, simulation process utilizing software tools.
Land area
That portion of the package lead which is inside the package cavity and to which the bonding wire will be connected to make electrical contact with the die.
A condition where the output of a circuit has become fixed near one of the two voltage extremes and will no longer react to changes in the input signal. Latchup may be radiation induced, but can also result from voltage overstresses and other causes.
Lead bend
A torsion test for lead strength. The process whereby flatpack leads are reformed to facilitate mounting on a PC board.
Lead fatigue
Application of a repetitive bending force to the leads of sample devices to insure structural integrity of leads and packages.
Leadless package
An IC package that has no leads (pins). It instead uses metal pads at its outer edge to make contact with the printed circuit board.
Line width
A measure of the horizontal dimensions of surface features of a semiconductor die, such as the separation between gate and drain diffusions on an MOS die.
Medium Scale Integratio – MSI devices are generally accepted to be those that contain 12 or more gate equivalents, but less than 100.
Moisture Sensitivity Level relates to the packaging and handling precautions for some semiconductors. The MSL is an electronic standard for the time period in which a moisture sensitive device can be exposed to ambient room conditions (approximately 30°C/60%RH).
Mean Time Between Failure – The average number of operating hours after a device has failed that would pass before the next device failure would be expected to occur.
A semiconductor building block containing a relatively complex electronic function that can be combined through CAD with other cells to perform a complex function with less design effort than a complete “ground-up” design.
Majority carrier
The mobile charge carrier (hole or electron) that predominates in a semiconductor material. When a channel is created within the silicon, the channel will normally result from a change of majority carrier.
A patterned screen of any of several materials used to expose selected areas of a semiconductor covered with a light-sensitive photoresist to polymerizing light during the fabrication process.
Mechanical shock
An impact-type shock test to stress die attach, wire bonds, and seal integrity, normally performed on a sample basis.
Metal gate
An MOS process fabricated with a metal (usually aluminum) as the gate electrode.
A very small crack within the metal or other material of a semiconductor device, typically not detectable using optical magnification. In the metallization area, microcracks most typically occur at contact steps. Microcracks can lead to discontinuities in the circuitry.
A unit of length. 106µ= 1 m (meter). [Note: µ as a symbol of length should not be confused with µ used as a prefix to indicate microunits, such as µA (microamps) or µV microvolts). A micron is one micrometer.
Mixed Signal ASIC
An Application Specific Integrated Circuit (ASIC), that contains both analog and digital circuits
Molded device
A device which is completely encapsulated in epoxy or an alternate molding compound, that is, with no internal cavity.
Monolithic device
A device whose circuitry is completed contained on a single die or chip.
An MOS process in which MOS transistors are formed by bridging two adjacent N-type diffusions (source and drain) with a dielectric (gate). When the source and the substrate are grounded and a positive voltage is applied to the gate, a conductive sheet of negative charge (N-channel) is created in the surface of the substrate under the dielectric.
Semiconductor material in which the majority carriers are electrons and are therefore negative.
Nonvolatile Random Access Memory
NPN transistor
A junction transistor constructed by placing a P-type base between an N-type emitter and an N-type collector. The emitter is normally negative with respect to the base and the collector is normally positive with respect to the base.
Non-Recurring Engineering, refers to the one-time cost of researching, developing, designing, and testing a new product
Non-Volatile Memory (NVM)
Nonvolatile Memory is memory which retains its stored value when power is removed.
Non-destructive bond pull
Pull stressing of all wires on all devices or a sample of devices from a given lot to a pull force which is lower than the minimum pull force limit imposed for destructive bond pull.
Operating life
Burn-in (that is, exposure to high temperature with electrical bias applied) performed for extended duration . Normally a sample test.
Oxide isolation
The separation of circuit elements on a semiconductor device through the construction of a barrier oxide between the elements (not to be confused with dielectric isolation, in which the isolation passes completely under the circuit element.
An MOS process in which MOS transistors are formed by bridging two adjacent P-type diffusions (source and drain) with a dielectric (gate). When the source and the substrate are grounded and a negative voltage is applied to the gate, a conductive sheet of positive charge (P-channel) is created in the surface of the substrate under the dielectric.
Semiconductor material in which the majority carriers are holes and are therefore positive.
Perfect Defect Allowable, the maximum percentage of a lot which may fail a 100% screening step without rejecting the lot. The PDA is predicted on the possibility that a failure mechanism which appears in an abnormally high percentage of a lot might appear at a later time in the balance of the lot. It should, therefore, not be used for screens where all defective devices can be observed and removed (such as internal visual or X-ray).
Phase Locked Loop. Mixed-signal block used to adjust phase of output with respect to the input.  Used in clock generation and signal demodulation.
PNP transistor
A junction transistor constructed by placing an N-type base between a P-type emitter and a P-type collector. The emitter is normally positive with respect to the base and the collector is normally negative with respect to the base.
Parts-per-million. A measurement scale for defect rates in components or impurity levels in materials.
Programmable Read-Only Memory. A memory device whose stored data content is established on an individual device basis through a programming process (usually involving the blowing of fuse links on the surface of the die). Unlike EPROMs and EEPROMs, PROMs cannot be erased and reprogrammed.
Packaging density
For integrated circuits, the number of semiconductor elements per unit area of chip size, frequently expressed in terms of number of gate equivalents.
Parasitic device or element
An interaction between diffused circuit elements. A good example of a parasitic would be the collector series resistance (RSAT) of a transistor and the associated capacitance of the collector-to-substrate junction.
Particle Count
A measurement scale for gas or liquid cleanliness, normally stated in parts per cubic foot. For example, a Class 10 working area would be one which contained no more than 10 particles greater than one micron in size per cubic foot of air.
The surface coating of the die (usually thermally grown silicon dioxide, Si02) through which contact and diffusion windows are opened.
Passive device
Devices such as resistors or capacitors which have no amplification or control characteristics.
Peripheral device
A device within a microprocessor device family whose function is required to support the operation of a CPU.
The listing or diagram description of the functions assigned to the various package pins of a semiconductor device.
Small localized areas in the oxide layer with low dielectric strength, usually as a result of contamination.
Planar structure
A flat-surfaced device structure with the junctions terminating on a single plane.
Electrical test of semiconductor devices at the wafer level, so named because a metal probe is used to make electrical contact with each of the device’s bonding pads.
Protective device
A circuit element fabricated on a semiconductor device (usually adjacent to the device input) for the purpose of protecting portions of the device circuitry from transient overstress. A good example of a protective device would be an input diode on a CMOS device, which absorbs electrostatic discharge to prevent that discharge from rupturing the gate oxide.
A functional device for verification of the Integrated Circuit.
Qualification testing
Testing performed one time only on a sample basis to determine the suitability of a product or product family for usage against certain specifications or for certain programs.
Conformance to a set of predetermined design and workmanship standards. Quality and reliability are not synonymous.
Random Access Memory-A storage device in which the ability to access a randomly selected bit of stored data is independent of either the timing of the most recent access of that bit or the location of the most recently addressed bit.
Radio Frequency, The range of electromagnetic frequencies above the audio range and below infrared light (from 10 kHz to 300 GHz.
Read Only Memory-A semiconductor device for storing data in permanent, nonerasable form, usually accomplished through the configuration of the metal mask pattern during wafer fabrication.
Extruded Aluminum or Plastic Tubes for Component / Device Handling.
Reject number
For a sample test, the number of failed devices which will cause lot rejection. This will normally be one higher than the accept number.
The anticipated lifetime of a device, how long it can be expected to “survive” in the user’s system. This is normally defined as a failure rate (percent per 1000 hours) or as an MTBF (Mean Time Between Failures, expressed in hours).
A photomask used in the fabrication of a wafer
Scanning Electron Microscope Inspection, which allows magnification several magnitudes higher than could be achieved with an optical microscope. A scanning electron microscope is typically capable of resolution to 250 A or better and magnification of greater than 20000X.
Abbreviation for single-in-line package.
Surface Mounted Packaging.
Simulation Program with Integrated Circuit Emphasis, standard for electronic circuit simulation.
Small Scale Integration. SSI devices are those that contain less than 12 gate equivalents.
A device or devices randomly chosen from a lot of material. Sampling assumes that randomly selected devices will exhibit characteristics during testing that are typical of the lot as a whole.
Sampling Plan
A statistically derived set of sample sizes, accept numbers, and/or reject numbers which will confirm that a given lot of materials meets established AQLs or LTPDs.
Schematic Drawing
Diagram of an electrical or mechanical system.
Schottky barrier
A potential barrier formed between a metal and a semiconductor, frequently used in the creation of Schottky diodes.
100% testing of a device, as opposed to sampling
Scribe lane
The area separating two adjacent dice on a wafer through which the scribing tool will pass during the separation of the wafer into individual dice.
The process whereby the lid is fastened onto a cavity (or hermetic) type semiconductor device. Sealing methods include solder (whereby a metal lid is soldered to a metal seal ring), weld (where a metal lid is welded to a metal package base), and glass (or ceramic) seal (where a ceramic lid is fastened to a ceramic base with reflowed glass).
An element, such as silicon or germanium, that is the intermediate in electrical conductivity between the conductors and the insulators.
Application of a unique alphanumeric identifier to each unit of a lot of devices to afford traceability to variables data, individual radiographs, etc.
symbol Si, is the most commonly used basic building block of integrated circuits. Silicon is a semiconductor, which means that its electrical behavior is between that of a conductor and an insulator at room temperature. With the proper addition of dopant elements, p-n junctions can be formed on silicon. Useful electronic components and integrated circuits can be built from p-n junctions. Silicon is obtained by heating silicon dioxide (SiO2), or silica, with a reducing agent in a furnace. Silicon dioxide is the main component of ordinary sand.
Silicon gate
An MOS process fabricated with a polysilicon material as the gate electrode.
Single-in-line package
A package (either hermetic or molded) with all its leads emanating from one side of the package.
Soft error
An error of a nonpermanent nature introduced into a cell or cells of a memory device as a result of either voltage or current transients or radiation exposures. Although soft errors may be corrected, the data previously stored in the cell may not be retrievable.
The instructions which program or sequence the functioning of the hardware of a device or system. These instructions may be contained internally (in ROM, for example) or externally (on tape, disc, or any other suitable memory medium).
Solder dip
Dipping of the leads of devices into molten solder in order to later facilitate soldering of the devices to circuit boards. Sometimes inaccurately referred to as “tin dip.,
Solder seal
Semiconductor device sealing accomplished by soldering a metal lid to a metal seal ring.
Solderability testing
Immersion of the leads of sample devices in solder, followed by visual inspection to determine that the quality of the finish is such that it will accept an even coating of solder.
Source control drawing
Similar to a specification control drawing except that purchase of the specified devices from manufacturing sources other than those listed on the drawing is prohibited.
Source inspection
Surveillance or inspection by a customer’s quality representative or by a government inspector at the vendor’s facility of material being assembled or screened by that vendor.
Stabilization bake
Placement of devices in a chamber at elevated temperature (normally 150°C) without electrical bias in order to test the construction of the devices.
Standard Product
an integrated circuit that implements functions that appeals to a wide market. As opposed to ASICs that combine a collection of functions and designed by or for one customer.
Statistical quality control
A quality control system utilizing statistical analysis of process defect data to detect quality trends on a real time basis.
The physical material upon which an integrated circuit is fabricated or assembled. For a monolithic device, this would be the silicon of the chip; for a hybrid it would be the alumina or ceramic surface upon which the die and other elements are deposited.
Surface mounted packaging
Semiconductor packages mounted on the surface of a printed circuit board or other substrate material.
Surface states
Extra donors, acceptors, or traps, usually undesired, which may occur on a semiconductor surface because of crystal imperfections or contamination. These may vary with time.
Tape & Reel
Pocket carrier Tape with a protective Cover Tape that holds the device in place on a Reel.
Temperature cycle
A test whereby devices are stored for short periods alternately at high and low temperatures in gas filled chambers, with a maximum transfer time between chambers of one minute. This stresses device assembly because of the different thermal coefficients of expansion of the various materials used.
Thermal resistance
Normally stated in terms of °C/W, it is the indicator of the package’s ability to dissipate the heat generated by the chip during operation.
Thermal secondary breakdown
Burnout of a semiconductor junction area as the result of a reverse-bias voltage or current induced thermal runaway condition.
Thermal shock
Similar to Temperature Cycle except that the environments are liquid, and the transfer is immediate. Normally Performed for 15 cycles from 0°C to + 100°C, this is a much more severe stress of the package seal and is normally employed only on a sample basis
Measure of junction temperature dependency on power dissipation. Indicates junction temperature elevation above ambient temperature (i.e. air around package) given in °C/W.
Measure of junction temperature dependency on power dissipation. Indicates junction temperature elevation above package case temperature given in °C/W. Typically preferred over Theta-JA when heat sinks are used.
Thick film
Any coating thickness greater than 5 (5 X 104 A), typically formed by applying a liquid, solid, or paste coating through a screen or mask in a selective pattern.
Thin film
Any coating thickness less than 5µ (5 X 104 A), typically formed by vacuum depositing or sputtering.
Threshold voltage
The voltage level at which a device will recognize a falling or rising voltage as a change in logic state.
A mounting technique for semiconductor packages in which the device leads are passed through holes in the mounting surface. Attachment of leads may be accomplished with solder or with other mechanical means.
Tin dip
A term commonly misapplied to the solder dipping of device leads.
Junction Temperature.  Temperature of silicon die at the transistor junction.
Those characteristics of hardware or software which allow its transferal from one system to another system and to interface compatibly with the hardware and software of the new system.
Triboelectric effects
The creation of electrostatic charge that occurs when two surfaces contact and then separate, leaving one positively charged and the other negatively charged.
Trim and form
The step in the assembly process for devices assembled on a lead frame (such as flatpacks and dual-in-line packages) where the lead frame is trimmed off and the leads bent or formed into their specified positions.
Trimming Analog circuits
The use of floating gate MOS devices for trimming Analog circuits
Truth table
For a logic device, a table showing the output logic states that would result from each of the possible input logic combinations the device is designed to accept.
Ultra Large-Scale Intégration. A term applied to devices with complexity levels in excess of 10,000 gates.
Devices or processes in which current carrying areas and substrates are of similar polarities, usually MOS devices.
Very High-Speed Integrated Circuits. The acronym applied to the Department of Defense sponsored research and development program to advance the state of the art in semiconductor device speeds, densities, power consumption, and system effectiveness.
Very Large-Scale Integrated Circuits. VLSI devices are generally accepted to be those that contain more than 1000 gate equivalents, but less than 10,000.
Supply voltage that corresponds to a logic 0 rail.  Typically, 0V.
Variables data
Recorded parametric or delta values, traceable to individual devices, as opposed to lot data (or attributes data).
Voltage input high, representative of a logic 1 at an input.
Voltage input low, representative of a logic 0 at an input
Voltage output high, representative of a logic 1 on an output.
Voltage output low, representative of a logic 0 on an output.
Wafer fabrication
The process whereby semiconductor elements are manufactured on the surface of silicon wafers.
Wafer lot
A single lot of wafers processed through all processing steps including metallization together. A wafer run may consist of more than one device type, where the various device types differ only in the metallization pattern employed.
Wafer lot acceptance testing
Testing of an integrated circuit wafer lot to determine its acceptability for the assembly of Class S devices
Wafer probe
Or Wafer sort,a process of electrical testing with a set of microscopic contacts or probes called a Probe card are held in place with the wafer, vacuum-mounted on a Wafer Chuck, is moved into electrical contact. When a die (or array of dice) have been electrically tested the prober moves the wafer to the next die (or array) and the next test can start.
Waffle Packs
Waffle Pack is a form of packaging designed for use with parts that are either very small or unusual in shape. Waffle pack are embossed or pocketed trays, typically made of plastic, that resemble a breakfast waffle (hence the name).
Radiographic analysis of the construction of a device. This is a less useful technique for devices with aluminum bond wires since only die attach and seal defects can be evaluated. For devices with gold wire it is a more valuable screen as it can detect damage done to wires during centrifuge and other such tests, as well as most assembly defects.
The total number of devices which are electrically and mechanically within applicable specifications, expressed as a percentage of the total population.
Scroll to Top