************************************************************* * CSS555 TIMER MACROMODEL *********************** * Power setting = Micro *********************** * Trip levels = Standard (1/3, 2/3) *********************** * Internal timing cap = 5pF *********************** * 6/29/09 Rev 1.1 F.J. Bohac *********************** * Custom Silicon Solutions *********************** * Beta testing - J. Granville *********************** ************************************************************* * source CSS555_uPwr_StdLev * PINS 7 4 3 2 5 8 1 6 .SUBCKT CSS555 DISCHG RESETB TMR_OUT TRIGB VCTRL VDD VSS VTH * Reference voltage generators E_VDDBF VDDBF VSS VDD VSS 1 E_VDDHF VDD_HF VSS VDD VSS 0.5 * IDD Devices R_RBIAS VSS VDD 2.25Meg I_IBIAS N275889 VSS DC 1.4uA D_DN8A VDD N275897 DMOD D_DN8B N275897 N275889 DMOD D_DN8D VSS N275889 DMOD * ESD Clamp Diodes and Pad Caps D_DP2 TRIGB VDD DMOD D_DN2 VSS TRIGB DMOD C_CPD2 TRIGB VSS 5pF D_DP3 TMR_OUT VDD DMOD D_DN3 VSS TMR_OUT DMOD C_CPD3 TMR_OUT VSS 5pF D_DP4 RESETB VDD DMOD D_DN4 VSS RESETB DMOD C_CPD4 RESETB VSS 5pF D_DP5 VCTRL VDD DMOD D_DN5 VSS VCTRL DMOD C_CPD5 VCTRL VSS 5pF D_DP6 VTH VDD DMOD D_DN6 VSS VTH DMOD C_CPD6 VTH VSS 5pF D_DP7 DISCHG VDD DMOD D_DN7 VSS DISCHG DMOD C_CPD7 DISCHG VSS 5pF *1/3, 2/3 Resistor Divider R_R3 VCTRL VDD 2.5Meg R_R4 VLOW VCTRL 2.5Meg R_R5 VSS VLOW 2.5Meg * * Comparators with limiters E_CMP1 COMP1 VDD_HF VTH VCTRL 1000 E_CMP2 COMP2 VDD_HF VLOW TRIGB 1000 R_R1 COMP1_LIM COMP1 100K D_DL1P COMP1_LIM VDDBF DMOD D_DL1N VSS COMP1_LIM DMOD C_CD1 VSS COMP1_LIM 1pF R_R2 COMP2_LIM COMP2 100K C_CD2 VSS COMP2_LIM 1pF D_DL2P COMP2_LIM VDDBF DMOD D_DL2N VSS COMP2_LIM DMOD * Reset Input M_MP6 RESET RESETB VDD VDD PMOSMOD W=5u L=1u AD=10p AS=10p PD=14u + PS=14u M_MN6 RESET RESETB VSS VSS NMOSMOD W=2.5u L=1u AD=5p AS=5p PD=9u PS=9u * RS Flip Flop w Delay (NOR2 and NOR3) M_NOR2_MP21 NOR2_N1181941 NOR3D VDD VDD PMOSMOD W=5u L=1u AD=10p AS=10p + PD=14u PS=14u M_NOR2_MP22 NOR2 COMP2_LIM NOR2_N1181941 VDD PMOSMOD W=5u L=1u AD=10p + AS=10p PD=14u PS=14u M_NOR2_MN21 NOR2 NOR3D VSS VSS NMOSMOD W=2.5u L=1u AD=5p AS=5p PD=9u + PS=9u M_NOR2_MN22 NOR2 COMP2_LIM VSS VSS NMOSMOD W=2.5u L=1u AD=5p AS=5p + PD=9u PS=9u R_NR2D NOR2 NOR2D 100K C_NR2D NOR2D VSS 0.1pF M_NOR3_MP31 NOR3_N1173861 RESET VDD VDD PMOSMOD W=5u L=1u AD=10p AS=10p + PD=14u PS=14u M_NOR3_MP32 NOR3_N1173542 COMP1_LIM NOR3_N1173861 VDD PMOSMOD W=5u L=1u + AD=10p AS=10p PD=14u PS=14u M_NOR3_MP33 NOR3 NOR2D NOR3_N1173542 VDD PMOSMOD W=5u L=1u AD=10p AS=10p + PD=14u PS=14u M_NOR3_MN31 NOR3 RESET VSS VSS NMOSMOD W=2.5u L=1u AD=5p AS=5p PD=9u + PS=9u M_NOR3_MN32 NOR3 COMP1_LIM VSS VSS NMOSMOD W=2.5u L=1u AD=5p AS=5p + PD=9u PS=9u M_NOR3_MN33 NOR3 NOR2D VSS VSS NMOSMOD W=2.5u L=1u AD=5p AS=5p PD=9u + PS=9u R_NR3D NOR3 NOR3D 100K C_NR3D NOR3D VSS 0.1pF * Delay model (RC) R_RDLY NOR3D NOR3 2Meg C_CDLY VSS NOR3D 1pF * Pre-driver M_PDRV_MP41 PDRV_INB NOR3_DLY VDDBF VDD PMOSMOD W=5u L=1u AD=10p AS=10p + PD=14u PS=14u M_PDRV_MN41 PDRV_INB NOR3_DLY VSS VSS NMOSMOD W=2.5u L=1u AD=5p AS=5p + PD=9u PS=9u M_PDRV_MP42 PDRV_OUT PDRV_INB VDD VDD PMOSMOD W=16u L=1u AD=32p AS=32p + PD=36u PS=36u M_PDRV_MN42 PDRV_OUT PDRV_INB VSS VSS NMOSMOD W=7u L=1u AD=14p AS=14p + PD=18u PS=18u M_PDRV_MP43 PDOUT PDRV_OUT VDD VDD PMOSMOD W=50u L=1u AD=100p AS=100p + PD=104u PS=104u M_PDRV_MN43 PDOUT PDRV_OUT VSS VSS NMOSMOD W=20u L=1u AD=40p AS=40p + PD=44u PS=44u * Output drivers (Timer Out and Discharge) M_MN4 TMR_OUT PDOUT VSS VSS NMOSMOD W=175u L=1u AD=350p AS=350p PD=354u + PS=354u M_MP4 TMR_OUT PDOUT VDD VDD PMOSMOD W=500u L=1u AD=1000p AS=1000p + PD=1004u PS=1004u M_MN5 DISCHG PDOUT VSS VSS NMOSMOD W=400u L=1u AD=800p AS=800p PD=804u + PS=804u * Internal timing capacitor C_CTI VSS VTH 5pF * CSS555 Simulation Models * .MODEL DMOD D (LEVEL = 1 RS = 5) .MODEL NMOSMOD NMOS (LEVEL = 1 VTO = 0.75 KP = 7.00E-5 RD = 5.00 + CGBO = 1P, CGDO = 1P, CGSO = 1P) .MODEL PMOSMOD PMOS (LEVEL = 1 VTO = -0.75 KP = 2.60E-5 RD = 5.00 + CGBO = 1P, CGDO = 1P, CGSO = 1P) .ENDS ************************************************************* * CSS555 TIMER MACROMODEL *********************** * Power setting = Micro *********************** * Trip levels = Low V (10%, 90%) *********************** * Internal timing cap = 5pF *********************** * 6/29/09 Rev 1.1 F.J. Bohac *********************** * Custom Silicon Solutions *********************** * Beta testing - J. Granville *********************** ************************************************************* * source CSS555_uPwr_LowVLev * PINS 7 4 3 2 5 8 1 6 .SUBCKT CSS555 DISCHG RESETB TMR_OUT TRIGB VCTRL VDD VSS VTH * Reference voltage generators E_VDDBF VDDBF VSS VDD VSS 1 E_VDDHF VDD_HF VSS VDD VSS 0.5 * IDD Devices R_RBIAS VSS VDD 2.25Meg I_IBIAS N275889 VSS DC 1.4uA D_DN8A VDD N275897 DMOD D_DN8B N275897 N275889 DMOD D_DN8D VSS N275889 DMOD * ESD Clamp Diodes and Pad Caps D_DP2 TRIGB VDD DMOD D_DN2 VSS TRIGB DMOD C_CPD2 TRIGB VSS 5pF D_DP3 TMR_OUT VDD DMOD D_DN3 VSS TMR_OUT DMOD C_CPD3 TMR_OUT VSS 5pF D_DP4 RESETB VDD DMOD D_DN4 VSS RESETB DMOD C_CPD4 RESETB VSS 5pF D_DP5 VCTRL VDD DMOD D_DN5 VSS VCTRL DMOD C_CPD5 VCTRL VSS 5pF D_DP6 VTH VDD DMOD D_DN6 VSS VTH DMOD C_CPD6 VTH VSS 5pF D_DP7 DISCHG VDD DMOD D_DN7 VSS DISCHG DMOD C_CPD7 DISCHG VSS 5pF * 10%, 90% Resistor Divider R_R3 VCTRL VDD 750K R_R4 VLOW VCTRL 6.0Meg R_R5 VSS VLOW 750K * * Comparators with limiters E_CMP1 COMP1 VDD_HF VTH VCTRL 1000 E_CMP2 COMP2 VDD_HF VLOW TRIGB 1000 R_R1 COMP1_LIM COMP1 100K D_DL1P COMP1_LIM VDDBF DMOD D_DL1N VSS COMP1_LIM DMOD C_CD1 VSS COMP1_LIM 1pF R_R2 COMP2_LIM COMP2 100K C_CD2 VSS COMP2_LIM 1pF D_DL2P COMP2_LIM VDDBF DMOD D_DL2N VSS COMP2_LIM DMOD * Reset Input M_MP6 RESET RESETB VDD VDD PMOSMOD W=5u L=1u AD=10p AS=10p PD=14u + PS=14u M_MN6 RESET RESETB VSS VSS NMOSMOD W=2.5u L=1u AD=5p AS=5p PD=9u PS=9u * RS Flip Flop w Delay (NOR2 and NOR3) M_NOR2_MP21 NOR2_N1181941 NOR3D VDD VDD PMOSMOD W=5u L=1u AD=10p AS=10p + PD=14u PS=14u M_NOR2_MP22 NOR2 COMP2_LIM NOR2_N1181941 VDD PMOSMOD W=5u L=1u AD=10p + AS=10p PD=14u PS=14u M_NOR2_MN21 NOR2 NOR3D VSS VSS NMOSMOD W=2.5u L=1u AD=5p AS=5p PD=9u + PS=9u M_NOR2_MN22 NOR2 COMP2_LIM VSS VSS NMOSMOD W=2.5u L=1u AD=5p AS=5p + PD=9u PS=9u R_NR2D NOR2 NOR2D 100K C_NR2D NOR2D VSS 0.1pF M_NOR3_MP31 NOR3_N1173861 RESET VDD VDD PMOSMOD W=5u L=1u AD=10p AS=10p + PD=14u PS=14u M_NOR3_MP32 NOR3_N1173542 COMP1_LIM NOR3_N1173861 VDD PMOSMOD W=5u L=1u + AD=10p AS=10p PD=14u PS=14u M_NOR3_MP33 NOR3 NOR2D NOR3_N1173542 VDD PMOSMOD W=5u L=1u AD=10p AS=10p + PD=14u PS=14u M_NOR3_MN31 NOR3 RESET VSS VSS NMOSMOD W=2.5u L=1u AD=5p AS=5p PD=9u + PS=9u M_NOR3_MN32 NOR3 COMP1_LIM VSS VSS NMOSMOD W=2.5u L=1u AD=5p AS=5p + PD=9u PS=9u M_NOR3_MN33 NOR3 NOR2D VSS VSS NMOSMOD W=2.5u L=1u AD=5p AS=5p PD=9u + PS=9u R_NR3D NOR3 NOR3D 100K C_NR3D NOR3D VSS 0.1pF * Delay model (RC) R_RDLY NOR3_DLY NOR3 2Meg C_CDLY VSS NOR3_DLY 1pF * Pre-driver M_PDRV_MP41 PDRV_INB NOR3_DLY VDDBF VDD PMOSMOD W=5u L=1u AD=10p AS=10p + PD=14u PS=14u M_PDRV_MN41 PDRV_INB NOR3_DLY VSS VSS NMOSMOD W=2.5u L=1u AD=5p AS=5p + PD=9u PS=9u M_PDRV_MP42 PDRV_OUT PDRV_INB VDD VDD PMOSMOD W=16u L=1u AD=32p AS=32p + PD=36u PS=36u M_PDRV_MN42 PDRV_OUT PDRV_INB VSS VSS NMOSMOD W=7u L=1u AD=14p AS=14p + PD=18u PS=18u M_PDRV_MP43 PDOUT PDRV_OUT VDD VDD PMOSMOD W=50u L=1u AD=100p AS=100p + PD=104u PS=104u M_PDRV_MN43 PDOUT PDRV_OUT VSS VSS NMOSMOD W=20u L=1u AD=40p AS=40p + PD=44u PS=44u * Output drivers (Timer Out and Discharge) M_MN4 TMR_OUT PDOUT VSS VSS NMOSMOD W=175u L=1u AD=350p AS=350p PD=354u + PS=354u M_MP4 TMR_OUT PDOUT VDD VDD PMOSMOD W=500u L=1u AD=1000p AS=1000p + PD=1004u PS=1004u M_MN5 DISCHG PDOUT VSS VSS NMOSMOD W=400u L=1u AD=800p AS=800p PD=804u + PS=804u * Internal timing capacitor C_CTI VSS VTH 5pF * CSS555 Simulation Models * .MODEL DMOD D (LEVEL = 1 RS = 5) .MODEL NMOSMOD NMOS (LEVEL = 1 VTO = 0.75 KP = 7.00E-5 RD = 5.00 + CGBO = 1P, CGDO = 1P, CGSO = 1P) .MODEL PMOSMOD PMOS (LEVEL = 1 VTO = -0.75 KP = 2.60E-5 RD = 5.00 + CGBO = 1P, CGDO = 1P, CGSO = 1P) .ENDS ************************************************************* * CSS555 TIMER MACROMODEL *********************** * Power setting = Low *********************** * Trip levels = Standard (1/3, 2/3) *********************** * Internal timing cap = 5pF *********************** * 6/29/09 Rev 1.1 F.J. Bohac *********************** * Custom Silicon Solutions *********************** * Beta testing - J. Granville *********************** ************************************************************* * source CSS555_LowPwr_StdLev * PINS 7 4 3 2 5 8 1 6 .SUBCKT CSS555 DISCHG RESETB TMR_OUT TRIGB VCTRL VDD VSS VTH * Reference voltage generators E_VDDBF VDDBF VSS VDD VSS 1 E_VDDHF VDD_HF VSS VDD VSS 0.5 * IDD Devices R_RBIAS VSS VDD 400K I_IBIAS N275889 VSS DC 9.3uA D_DN8A VDD N275897 DMOD D_DN8B N275897 N275889 DMOD D_DN8D VSS N275889 DMOD * ESD Clamp Diodes and Pad Caps D_DP2 TRIGB VDD DMOD D_DN2 VSS TRIGB DMOD C_CPD2 TRIGB VSS 5pF D_DP3 TMR_OUT VDD DMOD D_DN3 VSS TMR_OUT DMOD C_CPD3 TMR_OUT VSS 5pF D_DP4 RESETB VDD DMOD D_DN4 VSS RESETB DMOD C_CPD4 RESETB VSS 5pF D_DP5 VCTRL VDD DMOD D_DN5 VSS VCTRL DMOD C_CPD5 VCTRL VSS 5pF D_DP6 VTH VDD DMOD D_DN6 VSS VTH DMOD C_CPD6 VTH VSS 5pF D_DP7 DISCHG VDD DMOD D_DN7 VSS DISCHG DMOD C_CPD7 DISCHG VSS 5pF *1/3, 2/3 Resistor Divider R_R3 VCTRL VDD 2.5Meg R_R4 VLOW VCTRL 2.5Meg R_R5 VSS VLOW 2.5Meg * * Comparators with limiters E_CMP1 COMP1 VDD_HF VTH VCTRL 1000 E_CMP2 COMP2 VDD_HF VLOW TRIGB 1000 R_R1 COMP1_LIM COMP1 100K D_DL1P COMP1_LIM VDDBF DMOD D_DL1N VSS COMP1_LIM DMOD C_CD1 VSS COMP1_LIM 1pF R_R2 COMP2_LIM COMP2 100K C_CD2 VSS COMP2_LIM 1pF D_DL2P COMP2_LIM VDDBF DMOD D_DL2N VSS COMP2_LIM DMOD * Reset Input M_MP6 RESET RESETB VDD VDD PMOSMOD W=5u L=1u AD=10p AS=10p PD=14u + PS=14u M_MN6 RESET RESETB VSS VSS NMOSMOD W=2.5u L=1u AD=5p AS=5p PD=9u PS=9u * RS Flip Flop w Delay (NOR2 and NOR3) M_NOR2_MP21 NOR2_N1181941 NOR3D VDD VDD PMOSMOD W=5u L=1u AD=10p AS=10p + PD=14u PS=14u M_NOR2_MP22 NOR2 COMP2_LIM NOR2_N1181941 VDD PMOSMOD W=5u L=1u AD=10p + AS=10p PD=14u PS=14u M_NOR2_MN21 NOR2 NOR3D VSS VSS NMOSMOD W=2.5u L=1u AD=5p AS=5p PD=9u + PS=9u M_NOR2_MN22 NOR2 COMP2_LIM VSS VSS NMOSMOD W=2.5u L=1u AD=5p AS=5p + PD=9u PS=9u R_NR2D NOR2 NOR2D 100K C_NR2D NOR2D VSS 0.1pF M_NOR3_MP31 NOR3_N1173861 RESET VDD VDD PMOSMOD W=5u L=1u AD=10p AS=10p + PD=14u PS=14u M_NOR3_MP32 NOR3_N1173542 COMP1_LIM NOR3_N1173861 VDD PMOSMOD W=5u L=1u + AD=10p AS=10p PD=14u PS=14u M_NOR3_MP33 NOR3 NOR2D NOR3_N1173542 VDD PMOSMOD W=5u L=1u AD=10p AS=10p + PD=14u PS=14u M_NOR3_MN31 NOR3 RESET VSS VSS NMOSMOD W=2.5u L=1u AD=5p AS=5p PD=9u + PS=9u M_NOR3_MN32 NOR3 COMP1_LIM VSS VSS NMOSMOD W=2.5u L=1u AD=5p AS=5p + PD=9u PS=9u M_NOR3_MN33 NOR3 NOR2D VSS VSS NMOSMOD W=2.5u L=1u AD=5p AS=5p PD=9u + PS=9u R_NR3D NOR3 NOR3D 100K C_NR3D NOR3D VSS 0.1pF * Delay model (RC) R_RDLY NOR3_DLY NOR3 500K C_CDLY VSS NOR3_DLY 1pF * Pre-driver M_PDRV_MP41 PDRV_INB NOR3_DLY VDDBF VDD PMOSMOD W=5u L=1u AD=10p AS=10p + PD=14u PS=14u M_PDRV_MN41 PDRV_INB NOR3_DLY VSS VSS NMOSMOD W=2.5u L=1u AD=5p AS=5p + PD=9u PS=9u M_PDRV_MP42 PDRV_OUT PDRV_INB VDD VDD PMOSMOD W=16u L=1u AD=32p AS=32p + PD=36u PS=36u M_PDRV_MN42 PDRV_OUT PDRV_INB VSS VSS NMOSMOD W=7u L=1u AD=14p AS=14p + PD=18u PS=18u M_PDRV_MP43 PDOUT PDRV_OUT VDD VDD PMOSMOD W=50u L=1u AD=100p AS=100p + PD=104u PS=104u M_PDRV_MN43 PDOUT PDRV_OUT VSS VSS NMOSMOD W=20u L=1u AD=40p AS=40p + PD=44u PS=44u * Output drivers (Timer Out and Discharge) M_MN4 TMR_OUT PDOUT VSS VSS NMOSMOD W=175u L=1u AD=350p AS=350p PD=354u + PS=354u M_MP4 TMR_OUT PDOUT VDD VDD PMOSMOD W=500u L=1u AD=1000p AS=1000p + PD=1004u PS=1004u M_MN5 DISCHG PDOUT VSS VSS NMOSMOD W=400u L=1u AD=800p AS=800p PD=804u + PS=804u * Internal timing capacitor C_CTI VSS VTH 5pF * CSS555 Simulation Models * .MODEL DMOD D (LEVEL = 1 RS = 5) .MODEL NMOSMOD NMOS (LEVEL = 1 VTO = 0.75 KP = 7.00E-5 RD = 5.00 + CGBO = 1P, CGDO = 1P, CGSO = 1P) .MODEL PMOSMOD PMOS (LEVEL = 1 VTO = -0.75 KP = 2.60E-5 RD = 5.00 + CGBO = 1P, CGDO = 1P, CGSO = 1P) .ENDS ************************************************************* * CSS555 TIMER MACROMODEL *********************** * Power setting = Low *********************** * Trip levels = Low V (10%, 90%) *********************** * Internal timing cap = 5pF *********************** * 6/29/09 Rev 1.1 F.J. Bohac *********************** * Custom Silicon Solutions *********************** * Beta testing - J. Granville *********************** ************************************************************* * source CSS555_LowPwr_LowVLev * PINS 7 4 3 2 5 8 1 6 .SUBCKT CSS555 DISCHG RESETB TMR_OUT TRIGB VCTRL VDD VSS VTH * Reference voltage generators E_VDDBF VDDBF VSS VDD VSS 1 E_VDDHF VDD_HF VSS VDD VSS 0.5 * IDD Devices R_RBIAS VSS VDD 400K I_IBIAS N275889 VSS DC 9.3uA D_DN8A VDD N275897 DMOD D_DN8B N275897 N275889 DMOD D_DN8D VSS N275889 DMOD * ESD Clamp Diodes and Pad Caps D_DP2 TRIGB VDD DMOD D_DN2 VSS TRIGB DMOD C_CPD2 TRIGB VSS 5pF D_DP3 TMR_OUT VDD DMOD D_DN3 VSS TMR_OUT DMOD C_CPD3 TMR_OUT VSS 5pF D_DP4 RESETB VDD DMOD D_DN4 VSS RESETB DMOD C_CPD4 RESETB VSS 5pF D_DP5 VCTRL VDD DMOD D_DN5 VSS VCTRL DMOD C_CPD5 VCTRL VSS 5pF D_DP6 VTH VDD DMOD D_DN6 VSS VTH DMOD C_CPD6 VTH VSS 5pF D_DP7 DISCHG VDD DMOD D_DN7 VSS DISCHG DMOD C_CPD7 DISCHG VSS 5pF * 10%, 90% Resistor Divider R_R3 VCTRL VDD 750K R_R4 VLOW VCTRL 6.0Meg R_R5 VSS VLOW 750K * * Comparators with limiters E_CMP1 COMP1 VDD_HF VTH VCTRL 1000 E_CMP2 COMP2 VDD_HF VLOW TRIGB 1000 R_R1 COMP1_LIM COMP1 100K D_DL1P COMP1_LIM VDDBF DMOD D_DL1N VSS COMP1_LIM DMOD C_CD1 VSS COMP1_LIM 1pF R_R2 COMP2_LIM COMP2 100K C_CD2 VSS COMP2_LIM 1pF D_DL2P COMP2_LIM VDDBF DMOD D_DL2N VSS COMP2_LIM DMOD * Reset Input M_MP6 RESET RESETB VDD VDD PMOSMOD W=5u L=1u AD=10p AS=10p PD=14u + PS=14u M_MN6 RESET RESETB VSS VSS NMOSMOD W=2.5u L=1u AD=5p AS=5p PD=9u PS=9u * RS Flip Flop w Delay (NOR2 and NOR3) M_NOR2_MP21 NOR2_N1181941 NOR3D VDD VDD PMOSMOD W=5u L=1u AD=10p AS=10p + PD=14u PS=14u M_NOR2_MP22 NOR2 COMP2_LIM NOR2_N1181941 VDD PMOSMOD W=5u L=1u AD=10p + AS=10p PD=14u PS=14u M_NOR2_MN21 NOR2 NOR3D VSS VSS NMOSMOD W=2.5u L=1u AD=5p AS=5p PD=9u + PS=9u M_NOR2_MN22 NOR2 COMP2_LIM VSS VSS NMOSMOD W=2.5u L=1u AD=5p AS=5p + PD=9u PS=9u R_NR2D NOR2 NOR2D 100K C_NR2D NOR2D VSS 0.1pF M_NOR3_MP31 NOR3_N1173861 RESET VDD VDD PMOSMOD W=5u L=1u AD=10p AS=10p + PD=14u PS=14u M_NOR3_MP32 NOR3_N1173542 COMP1_LIM NOR3_N1173861 VDD PMOSMOD W=5u L=1u + AD=10p AS=10p PD=14u PS=14u M_NOR3_MP33 NOR3 NOR2D NOR3_N1173542 VDD PMOSMOD W=5u L=1u AD=10p AS=10p + PD=14u PS=14u M_NOR3_MN31 NOR3 RESET VSS VSS NMOSMOD W=2.5u L=1u AD=5p AS=5p PD=9u + PS=9u M_NOR3_MN32 NOR3 COMP1_LIM VSS VSS NMOSMOD W=2.5u L=1u AD=5p AS=5p + PD=9u PS=9u M_NOR3_MN33 NOR3 NOR2D VSS VSS NMOSMOD W=2.5u L=1u AD=5p AS=5p PD=9u + PS=9u R_NR3D NOR3 NOR3D 100K C_NR3D NOR3D VSS 0.1pF * Delay model (RC) R_RDLY NOR3_DLY NOR3 500K C_CDLY VSS NOR3_DLY 1pF * Pre-driver M_PDRV_MP41 PDRV_INB NOR3_DLY VDDBF VDD PMOSMOD W=5u L=1u AD=10p AS=10p + PD=14u PS=14u M_PDRV_MN41 PDRV_INB NOR3_DLY VSS VSS NMOSMOD W=2.5u L=1u AD=5p AS=5p + PD=9u PS=9u M_PDRV_MP42 PDRV_OUT PDRV_INB VDD VDD PMOSMOD W=16u L=1u AD=32p AS=32p + PD=36u PS=36u M_PDRV_MN42 PDRV_OUT PDRV_INB VSS VSS NMOSMOD W=7u L=1u AD=14p AS=14p + PD=18u PS=18u M_PDRV_MP43 PDOUT PDRV_OUT VDD VDD PMOSMOD W=50u L=1u AD=100p AS=100p + PD=104u PS=104u M_PDRV_MN43 PDOUT PDRV_OUT VSS VSS NMOSMOD W=20u L=1u AD=40p AS=40p + PD=44u PS=44u * Output drivers (Timer Out and Discharge) M_MN4 TMR_OUT PDOUT VSS VSS NMOSMOD W=175u L=1u AD=350p AS=350p PD=354u + PS=354u M_MP4 TMR_OUT PDOUT VDD VDD PMOSMOD W=500u L=1u AD=1000p AS=1000p + PD=1004u PS=1004u M_MN5 DISCHG PDOUT VSS VSS NMOSMOD W=400u L=1u AD=800p AS=800p PD=804u + PS=804u * Internal timing capacitor C_CTI VSS VTH 5pF * CSS555 Simulation Models * .MODEL DMOD D (LEVEL = 1 RS = 5) .MODEL NMOSMOD NMOS (LEVEL = 1 VTO = 0.75 KP = 7.00E-5 RD = 5.00 + CGBO = 1P, CGDO = 1P, CGSO = 1P) .MODEL PMOSMOD PMOS (LEVEL = 1 VTO = -0.75 KP = 2.60E-5 RD = 5.00 + CGBO = 1P, CGDO = 1P, CGSO = 1P) .ENDS